1. Field of the Invention
The present invention relates to a rod assembly for providing a plurality of wafers used for electronic devices by slicing, as well as a method of producing wafers used for electronic devices.
2. Description of the Background Art
Production steps for typical wafers used for electronic devices employed so far are to be explained referring to FIGS. 31 through 33.
At first, a Si single crystal ingot 1 is prepared as shown in FIG. 31. For obtaining a plurality of Si single crystal wafers each of an identical diameter, the outer circumference of the Si single crystal ingot 1 is shaped into a regular cylindrical form. Further, the upper end and the lower end in the longitudinal direction of the Si single crystal ingot 1 are removed. As shown in FIG. 32, a planar portion 3 extended in the longitudinal direction is formed to the Si single crystal rod 2 shaped into the regular cylindrical form for indicating the direction of the crystallographic axis of the single crystals. Then, the rod 2 of Si single crystals is subjected to slicing, thereby providing a plurality of Si single crystal wafers 4 each of a thickness of several hundreds of micrometers. A plurality of wafers 4 thus obtained are shown in FIG. 33. The main surface 5 of the wafer 4 is mirror-finished by means of lapping and polishing. Referring to FIG. 34 illustrating the plan view of the wafer 4, a plurality of semiconductor integrated circuits 6 are formed on the main surface 5 of the wafer 4 in the subsequent steps.
As shown in FIG. 34, various advantages can be obtained by forming a plurality of semiconductor integrated circuits 6 on one wafer 4. Before the advent of semiconductor devices, individual electronic devices such as vacuum tubes, resistance elements and capacitance elements had to be manufactured, basically, one by one even if they are mass-produced mechanically. In addition, before the advent of the semiconductor integrated circuit, electronic circuits had to be constituted by individual operations mainly by means of soldering. For instance, operations for connecting copper wires by means of soldering, operations for connection individual devices to printed circuit boards by means of soldering, etc. were required respectively.
On the other hand, with the technique of forming a plurality of semiconductor integrated circuits on one identical wafer, a plurality of identical circuits can be formed at a same time on one wafer, basically, by photolithography techniques. Accordingly, the manufacturing cost per one identical circuit constitution is outstandingly reduced by the technique of forming a plurality of integrated circuits on one identical wafer as compared with the prior art techniques requiring individual operations as described above.
For forming a semiconductor integrated circuit, processing steps before and after the photolithography step described above have also been conducted on a single wafer or on pluralities of wafers at a time. This also contributes to the reduction of the manufacturing cost par one identical circuit constitution. Specifically, the photolithography step is preceded and followed by various steps such as an epitaxial step for laminating crystals on a Si single crystal wafer, an ion implantation step for introducing impurities into the single crystal wafer, a diffusion step for diffusing impurities introduced into the wafer, an oxidation step of applying an oxidative treatment to a specific region for selectively introducing impurities into the wafer or protecting the bonded surface, a CVD step, a metallizing step for forming electrodes or wirings, etc. These steps are applied not individually to each of the circuits but on every single crystal wafers or pluralities of the single crystal wafers.
As has been described above, the manufacturing cost per identical circuit can be reduced significantly by simultaneously forming a plurality of identical semiconductor integrated circuits on one identical single crystal wafer. For further reducing the manufacturing cost per one circuit the number of identical semiconductor integrated circuits that can be formed at a same time on the wafer may be increaesd. In order to realize this, there have been employed a method of reducing a chip area by miniaturizing the circuit structure and a method of increasing the area of the single crystal wafer by increasing the diameter of the wafer.
Miniaturization of the circuit has developed considerably for several years after the establishment of the semiconductor technology. The value of the minimum line width in the photolithography technique at the initial stage, which was greater than 10 .mu.m, has recently been reduced to a value of less than 1.0 .mu.m. In this case, the effect in view of the area is more than 100 times.
In the same way, there has been a considerable development in increasing the wafer diameter. The diameter of the wafer at about 1 inch level at the initial stage has recently been increased to about 10 inch level The area effect in this case is also of about 100 times. As a synergistic effect obtained from the development for the miniaturization of the circuit and that from the increase in the wafer diameter, the area effect is now about ten thousands of times. It is apparent that this provides one of the bases for the development of the semiconductor integrated circuits and the development of the electronic technology at present.
However, as compared with the technical progress of simultaneously forming a plurality of identical semiconductor integrated circuits, the progress in the miniaturization of circuits and the increase in the wafer diameter are relatively slow.
The leading principle for miniaturizing the minimum line width in the photolithography technology from the value greater than 10 .mu.m to the value of less than 1.0 .mu.m mainly consists in removal of defects. That is, for miniaturizing the circuits, it has been conducted to remove dusts present in the production steps, ensure the pattern accuracy by ensuring the mechanical accuracy for mask alignment upon photolithography, or eliminate defects or unnecessary impurities present in crystals or thin films. Accordingly, in order to realize them, not only the softwares for the steps have to be changed but also change of hardwares such as introduction of production facilities of higher performance has been required. That is, much investment in equipment cost is necessary on every reduction of design rules. In this way, if the production cost per identical circuit construction is intended to be reduced by the miniaturization of the circuits, the production cost can not be reduced as expected because of much investment in equipment.
In the design rules at present, there is a problem in the miniaturization at a submicron level of less than 1.0 .mu.m. As the miniaturization is developed further within such a level, various problems are actually brought about.
At first, in the same way as in the miniaturizing progress conducted so far, much investment in equipment is required along with the development of the miniaturization, as well as the number, size and amount of defects to be eliminated becomes higher. Accordingly, the cost performance in the production facility is worsened. That is, the ratio (increment in investment in equipment)/(circuit miniaturization rate) is increased.
Next, additional production steps are required and, accordingly, the production cost is increased. For instance, if circuit miniaturization is intended to attain by applying improvement to steric structures (three dimensional structures) rather than by miniaturizing the planar circuit constitution, this increases the number of production steps required per unit wafer such as addition of trenching steps or lamination steps.
Finally, there is a physical limit in view of the dimension for producing integrated circuits. For instance, as a light source for mask alignment by photolithography, UV-ray have usually been employed in the level of the existent design rules. However, since UV-rays bring about deflection or interference, such UV-rays can no more be used under the design rule at submicron level. Accordingly, use of radiation-rays will be necessitated as a light source for the mask alignment by photolithography.
In view of the foregoing, difficulty in the circuit production is increased as the present design rule (e.g. the minimum dimension permitted) is reduced. An extreme difficulty is expected for reducing the minimum line width in the photolithography from 1.0 .mu.m level to 0.1 .mu.m level, that is, to increase the area effect by 100 times. Under the design rule at a submicron level, the reduction for the cost of semiconductor integrated circuits in accordance with the reduction in the chip area by the circuit miniaturization is saturated. That is, further miniaturization will be accomplished at a cost which will preclude further reduction in cost per chip.
Increase in the wafer diameter is determined, at first, by the production technology for single crystal ingot. For Si single crystal wafers at a mass production level, the maximum diameter is 6 in. at present. The maximum diameter for Si single crystal wafers at a trial level is 10 inch. The leading principle for increasing the wafer diameter from 1 inch level to 10 inch level consists in the scale-up of the facilities and removal of defects. That is, for the production of single crystal ingots of larger diameter, a facility of greater scale corresponding to the size is inevitably necessary. Along with the increase in the diameter of single crystal ingots, defects caused by localized stresses, etc. are brought about. Then, in order to eliminate such defects. more accurate thermal and mechanical control are necessary upon production of single crystal ingots. For more accurate thermal and mechanical control, it is necessary to provide additional control steps and make the production facility per se more accurate. In this way, increase in the diameter of single crystal ingots has a technical limit and also involves a drawback that it increase the cost for the production facility.
The maximum diameter of Si single crystal ingots at the trial level is limited within a level of 10 inch because of the reasons as described above. Further, the increase in the diameter of the Si single crystal wafer have developed from 2 inch level only by each step of 1-2 inch because of the same reasons as described above. The foregoing difficulty in increased along with the increase in the ingot diameter. That is, an extreme difficulty is expected for increasing the maximum ingot diameter from the 10 inch level to the 20 inch level, that is, for increasing the area effect by four times. After all, reduction of the cost for the semiconductor integrated circuits in compliance with the increase in the area of the single crystal wafer by the increase in the ingot diameter is saturated. That is, capital costs of producing large diameter crystals offset economics of producing more chips per wafer at larger wafer diameters.
Furthermore, increase in the wafer diameter by the step of 1-2 inch results in additioned economical difficulty. That is, if wafers of larger diameter have once been put to practical use, the cost for the semiconductor integrated circuits produced by using such wafers is reduced as compared to the semiconductor integrated circuits produced so far by using prior wafers, that is, by using wafers of smaller diameter. Accordingly, wafers of smaller diameter employed so far lose their competitive power in the market. Thus, since there may occur such a situation that production facilities for those wafers having relatively smaller diameter have to be discarded before reasonable depreciation as the wafers of relatively large diameter are put to practical use, Si single crystal manufacturers can not easily put the increase for the wafer diameter to practical use. In addition, putting the increase in the wafer diameter to practical use requires production facilities for semiconductor integrated circuits in compliance with larger diameter wafers. That is, along with the increase in the wafer diameter, more investment in equipment is required.
As has been described above, if wafers of relatively larger diameter are put to practical use, semiconductor integrated circuits using wafers of smaller diameter employed so far lose their market competitive power. Accordingly, most of production facilities for semiconductor integrated circuits used for the wafers of relatively smaller diameter have to be discarded before reasonable depreciation or their use have to be interrupted in the first line. In view of such situations, manufacturers for semiconductor integrated circuits can not easily put the increase for the wafer diameter into practical use. The maximum diameter of Si single crystal wafers at a practical level is limited at present to 6 inch level although the maximum diameter of Si single crystal wafers is 10 inch at the trial level, because of the background as has been described above.
As has been described above, although the cost for semiconductor integrated circuits has been reduced up to now by the reduction of the chip area due to circuit miniaturization and by the increase in the area of the single crystal wafers by enlarging the wafer diameter, reduction in the cost have gradually been saturated at present.